芯片互联与高速接口硅后验证架构师（芯片平台） - 芯片研发
Core
End-to-end post-silicon EVB board-level validation and productization support for ByteDance's self-developed chips, ensuring validation quality for on-chip interconnects and high-speed interfaces.
Role type
Senior IC post-silicon validation architect (high-speed interconnects & SerDes)
Builds
Production-ready silicon chips with validated high-speed interfaces (PCIe, UCIe, CXL, etc.) and SerDes/PHY IP for data center AI clusters.
Domain
Semiconductor design, Data Center AI infrastructure, High-speed digital interfaces
Deliverable
production ML models
Required skills
Post-silicon board-level validation, Electrical Validation (EV), Signal Integrity Validation (SIV), Protocol consistency validation, SerDes/PHY IP initialization and calibration, High-speed interface protocol standards (PCIe/UCIe/CXL/NVLink), Test equipment operation (oscilloscopes, protocol analyzers), DFX, BIST, System margin and stability analysis
Preferred skills
Self-developed SerDes/UCIe PHY solutions, White-box post-silicon validation and tuning, Advanced packaging validation experience, AI cluster data flow understanding
Technologies
PCIe, UCIe, BoW, UALink, CXL, RDMA, NVLink, UEC, SerDes, PHY, IO, PLL, ADC, Retimer, Switch, LPO, NPO, CPO, FPGA, Silicon, EVB
Responsibilities
Define validation strategies, plans, and test cases for post-silicon validation; Execute electrical, signal integrity, and protocol validation on EVB boards; Troubleshoot and resolve issues related to high-speed interfaces and system stability; Analyze results and generate evaluation reports for productization.
Seniority
Senior, hands-on IC
