Director, SoC Design Verification and Virtual Platform Quality
Core
Define and execute a reuse-first verification strategy for SystemC models, RTL, IP, subsystems, SoCs, and Virtual Platforms to ensure pre-silicon software development and product evaluation.
Role type
Director, Design Verification and Virtual Platform Quality
Builds
Reusable SystemC/TLM models, integrated Virtual Platforms, and scalable SystemVerilog/UVM environments for automotive, industrial, infrastructure, and IoT industries.
Domain
Semiconductor Design Verification, SystemC modeling, Virtual Platforms, pre-silicon software development
Required skills
SystemVerilog, UVM, SystemC/TLM-2.0, RTL design, computer architecture, embedded processors, interconnects, memory systems, CI/CD, regression automation, program management, team leadership
Preferred skills
TLM-to-signal adapters, DPI interfaces, Python/C++ verification, formal verification, emulation, FPGA prototyping, AMBA AXI/AHB/APB, NoC, PCIe, CXL, Ethernet, USB, SPI, I²C, eSPI, UART, GPIO, memory controllers, commercial EDA tools
Technologies
SystemVerilog, UVM, SystemC, TLM-2.0, Python, C++, AMBA AXI, AHB, APB, NoC, PCIe, CXL, Ethernet, USB, SPI, I²C, eSPI, UART, GPIO
Responsibilities
Define verification strategy for SystemC/RTL/IP/SoC/Virtual Platforms; Lead global DV organization; Establish common verification architecture; Develop scalable UVM environments; Define functional-equivalence and timing-correlation methodologies; Drive verification planning from IP to full-platform; Build CI/CD regression systems; Lead complex debug and root-cause analysis; Own staffing and organizational development.
Seniority
Director, strategic leadership with hands-on technical direction
