Senior Digital Verification Engineer
Core
Lead end-to-end verification of complex IC blocks and systems, architecting UVM-based environments and driving verification closure.
Role type
Senior IC digital verification engineer
Builds
ASIC/IC chips for Automotive, Industrial, Infrastructure, and IoT
Domain
Semiconductor hardware design and verification
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, constrained-random testing, assertion-based verification (SVA), formal methods, digital design, regression frameworks
Preferred skills
Verilog, VHDL, Cadence Xcelium, eManager/vManager, third-party VIP evaluation
Technologies
SystemVerilog, UVM, Verilog, VHDL, Cadence Xcelium, eManager, vManager
Responsibilities
Architect and execute comprehensive verification strategies and test plans; Drive functional and code coverage to closure; Review design specifications for verification fitness; Partner with architecture, design, and software teams on hardware/software partitioning; Mentor junior engineers and optimize automation flows; Evaluate third-party verification IP and tools.
Seniority
Senior, hands-on IC
