Sr Staff Engineer, STA
Core
Own RTL-to-Gate conversion, constraint development, and timing closure to deliver high-performance, low-power chips.
Role type
Senior Staff Backend Design Expert (Static Timing Analysis & Logic Synthesis)
Builds
Optimized gate-level netlists and timing-closed silicon for automotive, industrial, infrastructure, and IoT SoCs/MCUs.
Domain
Semiconductor EDA / Digital Logic Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> physical/clinical work (Note: This is a hardware design role, mapping to 'physical/clinical work' is incorrect based on the schema options provided in the prompt instructions which seem to be a copy-paste error in the system prompt. However, strictly following the instruction 'one of: ...', none fit perfectly. The role is clearly 'product features' (chip design) or 'infrastructure' (EDA flow). Given the context of 'shipping chips', 'product features' is the closest semantic fit for the output artifact, though 'infrastructure' fits the EDA flow. Let's select 'product features' as the primary deliverable is the chip itself.