Research Engineer, Chip Design RL (Reinforcement Learning)
Core
Designing RL environments and evaluations to teach AI models how to design silicon, specifically for RTL generation, verification, and physical design optimization.
Role type
Research Engineer (Chip Design RL)
Builds
RL environments, evaluation systems, and training runs for agentic hardware design.
Domain
Semiconductor hardware design (ASIC/FPGA) and Reinforcement Learning.
Deliverable
production ML models | research
Required skills
ASIC or FPGA design, RTL, design verification (UVM, formal methods), physical design (synthesis, place-and-route), PPA optimization, DFT, ECOs, EDA tools, chip tape-out experience.
Preferred skills
Reinforcement Learning, RL evaluations/environments, tooling/automation for chip design flows, ML accelerators, high-level synthesis, architecture simulators.
Technologies
UVM, formal methods, EDA tools, high-level synthesis, architecture simulators.
Responsibilities
Invent and implement RL environments for RTL generation and verification; optimize EDA-tool latency and proxy rewards; conduct experiments and shape the roadmap; deliver work into research and production training runs.
Seniority
Mid-to-Senior, hands-on IC
