Sr Engineer, Design Verification
Core
Develop verification testbench components and environments for complex memory interface integrated circuits using System Verilog and UVM.
Role type
Senior IC Design Verification Engineer
Builds
Chip/module level verification environments for memory interface products
Domain
Semiconductor / Memory Interfaces (DDR4/DDR5/LPDDR5)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, verification planning, code coverage, functional coverage, assertions, cover groups, silicon debugging, regression testing
Preferred skills
DDR4/DDR5/LPDDR5/DIMM protocol knowledge, Object-oriented design concepts
Technologies
System Verilog, UVM
Responsibilities
Develop verification testbench components for chip/module level; Define and execute detailed verification plans; Debug tests, regression failures, and participate in silicon debugging; Achieve 100% verification completeness before tape-out
Seniority
Senior, hands-on IC
