[EMN] Senior IP Design Verification Engineer
Core
Own and execute Silicon IP based pre-silicon verifications (e.g., UCIe Interoperability) from planning through sign-off.
Role type
Senior IC design verification engineer (Silicon IP)
Builds
Silicon IP blocks and verification environments for automotive and industrial technology products
Domain
Semiconductor / ASIC/SoC design
Deliverable
production ML models | product features
Required skills
System Verilog, OVM/UVM methodologies, testbench development, regression analysis, coverage modeling, AXI VIP/protocol verification, gate-level simulation, timing constraint simulation, root cause analysis, debugging across IP boundaries
Preferred skills
UCIe verification experience, PCIe Gen3/4/5, USB3, DDR4/5, Ethernet, CSI2, I3C protocol knowledge
Technologies
System Verilog, OVM, UVM, AXI VIP, UCIe, PCIe, USB, DDR, Ethernet, CSI2, I3C
Responsibilities
Develop and maintain verification environments, testbenches, and test cases; Run simulations and regressions to analyze failures and debug issues; Track verification progress and report status with risk mitigation; Review verification results and ensure process compliance; Guide junior engineers on verification methodology and debugging approaches
Seniority
Senior, hands-on IC
