Senior Signal Integrity / Power Integrity (SI/PI) Engineer
Core
Design, simulate, and characterize high-speed interconnects (channels, vias, packages) for next-generation SerDes technologies (112G/224G/448G PAM4) in Ethernet and optical networking platforms.
Role type
Senior IC Signal Integrity / Power Integrity Hardware Engineer
Builds
High-density Ethernet and optical systems for hyperscale, AI, and cloud networking
Domain
Networking hardware, high-speed digital design, electromagnetics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
3D EM design and simulation, S-parameter and time-domain measurements, link-level analysis for advanced standards, 2.5D/3D EM solvers, lab skills with oscilloscopes/VNAs/TDRs/BERTs, familiarity with advanced PCB materials
Preferred skills
co-packaged optics, chiplet-based architectures, EMI/EMC considerations, thermal and mechanical effects on SI/PI performance, fabrication vendor collaboration
Technologies
Ansys HFSS, SiWave, Cadence Sigrity, Keysight ADS, Cadence SystemSI, Megtron 7, Tachyon 100G, SLP
Responsibilities
Perform 3D EM design and simulation of high-speed interconnects, Develop and validate test vehicles to characterize PCB materials and interconnects, Conduct S-parameter and time-domain measurements, Perform link-level analysis for advanced standards, Collaborate with hardware, mechanical, and packaging teams to optimize routing strategies, Research and prototype novel materials and low-loss interconnect topologies, Support bring-up and debug of production boards
Seniority
Senior, hands-on IC
