ASIC Design Engineer
Core
Design and implement Smart Edge SoCs for network control, security systems, and IIoT, focusing on micro-architecture, RTL coding, and performance optimization.
Role type
Senior IC ASIC/SoC Design Engineer
Builds
Smart Edge SoCs for network/systems control, management security systems, and IIoT
Domain
Semiconductor / Hardware Security / AI Infrastructure
Deliverable
production ML models | product features
Required skills
RTL logic design, Verilog coding, micro-architecture design, synthesis, timing closure, FPGA prototyping, interface protocol expertise (PCIe, USB, Ethernet, DDR, I2C, SPI, etc.), scripting (Perl, Python), tapeout experience
Preferred skills
Silicon bring-up and debug, repository management (Bitbucket/Jenkins), bug tracking (JIRA)
Technologies
Verilog, Perl, Python, HAPS, Veloce, PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART
Responsibilities
Develop SoC design and implementation; perform top-level and block-level performance, bandwidth, and power optimization; collaborate with Architecture, Verification, Physical Design, and Software teams; support test program development, chip validation, and production maturity
Seniority
Senior, hands-on IC
