Sr. Engineer, Design Enablement
Core
Develop and maintain design enablement methodologies, drive Lint/CDC/RDC signoff flows, and automate checks to ensure high-quality RTL design across teams.
Role type
Senior IC verification engineer (design enablement)
Builds
Robust design-quality methodologies and automated verification flows for RTL design teams
Domain
Semiconductor hardware design (RTL verification)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (design enablement flows)
Required skills
RTL design (Verilog/SystemVerilog), Lint/CDC/RDC flows, Tcl scripting, shell scripting
Preferred skills
Python
Technologies
Verilog, SystemVerilog, Tcl, Shell, Python
Responsibilities
Develop & maintain design enablement methodologies, Drive Lint/CDC/RDC signoff flows, Automate checks and design workflows, Collaborate with design teams to ensure high-quality RTL, Create guidelines and best practices
Seniority
Senior, hands-on IC
