Power-Domain Verification Lead
Core
Lead verification for power-aware simulations and RTL SoC/subsystem verification focusing on power domains, states, and transitions in Smart Edge SoCs.
Role type
Senior IC verification engineer (power-aware simulation)
Builds
RTL SoC/Subsystem verification flows for Smart Edge SoCs
Domain
Semiconductor / Hardware Verification / Low-Power Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, UPF (power intent modeling), power-aware simulation, RTL verification, gate-level simulation, directed and constrained-random test generation, assertion development, functional coverage, scripting (Make, Perl, Python, Shell), power domain analysis, reset behavior verification
Preferred skills
Debugging across RTL/UPF/testbench, collaboration with RTL and power architects
Technologies
SystemVerilog, UVM, UPF, ARM CPUs, Portable Stimulus, Formal verification flows
Responsibilities
Execute power-aware simulations and debug failures related to power intent; Integrate UPF with UVM testbenches and VIPs; Create directed and constrained-random tests for low-power scenarios; Verify power gating, isolation, retention save/restore, and reset behavior across power domains; Develop assertions and functional coverage for power states and transitions; Support power-aware regression and sign-off
Seniority
Senior, hands-on IC
