Silicon Validation Engineer
Core
Own silicon bring-up and validation from first power-on through production readiness for high-performance GenAI chips.
Role type
Senior silicon validation engineer (post-silicon bring-up)
Builds
Vertically integrated full-stack compute platforms for AGI training and inference
Domain
Semiconductor hardware / AI infrastructure
Deliverable
production ML models | physical/clinical work
Required skills
silicon validation, post-silicon bring-up, hardware emulation, SoC architecture, digital hardware, firmware-hardware interaction, complex failure debugging, lab platform operation, C/C++ code reading, Python scripting, RTL/specification reading
Preferred skills
pre-silicon validation, Cadence Palladium, SystemVerilog/UVM, first silicon bring-up, HBM/DDR/PCIe/CXL interfaces, JTAG/oscilloscope usage
Technologies
Cadence Palladium, SystemVerilog, UVM, C, C++, Python, RTL, JTAG, oscilloscopes, logic analyzers
Responsibilities
Execute validation plans for chip-level functionality and performance; Validate boot, reset, power management, memory, and interconnect; Debug complex failures using logs, traces, and waveforms; Collaborate with architecture, DV, and firmware teams; Define observability requirements and improve validation automation
Seniority
Senior, hands-on IC
