Staff SoC Verification Engineer (S)
Core
Develop and maintain SystemVerilog/UVM-based verification environments for ultra-efficient neuromorphic processors serving IoT, wearable, embedded, and automotive domains.
Role type
Staff SoC Verification Engineer
Builds
Neuromorphic microprocessors for edge AI
Domain
Semiconductor / Neuromorphic Computing / SoC Verification
Deliverable
production ML models
Required skills
SystemVerilog, UVM, constrained-random verification, embedded C, root-cause analysis, Python scripting, Linux/bash, EDA tools, verification architecture design, functional coverage modeling, mixed-language simulation, team leadership
Preferred skills
None stated
Technologies
SystemVerilog, UVM, Python, Linux, bash, commercial EDA tools
Responsibilities
Develop and maintain SystemVerilog/UVM-based verification environments at module and SoC level; Write test sequences and define functional coverage models; Debug simulation results using waveform tools; Drive constrained-random stimulus generation; Apply modern EDA tools to automate verification flows; Contribute to quality assurance and release-readiness
Seniority
Staff, hands-on IC with mentorship
