Working Student - RTL Design for SoC Fault Tolerance & Error Detection (f/m/div)
Core
Design and implement Error Correction Codes (ECC) and failure detection mechanisms for System-on-Chip (SoC) memory protection.
Role type
RTL Design Engineer (SoC Fault Tolerance)
Builds
SoC components with integrated error correction and fault detection
Domain
Semiconductor / Hardware Design
Required skills
Verilog, VHDL, Digital Design, Python, Linux, Git, Fault Simulation
Responsibilities
Design and implement ECC for memory protection, Develop and integrate failure detection mechanisms (watchdog timers, checksums), Utilize fault simulation to verify robustness, Coordinate with team on fault detection interfaces, Maintain technical documentation
