Senior Engineer Functional Verification (f/m/div)
Core
Senior Engineer Functional Verification on the R&D team, merging creativity with technical expertise to shape the future of technology and drive groundbreaking projects.
Role type
Senior IC functional verification engineer (SoC/IP)
Builds
IP and SoC verification environments and flows
Domain
Semiconductor, power systems, IoT, wireless/high-speed communication
Required skills
SystemVerilog, UVM, OVM, verification environment development, debugging, functional coverage analysis, AI application in verification methodologies
Preferred skills
German language skills
Technologies
SystemVerilog, UVM, OVM
Responsibilities
Contribute hands-on to IP and SoC verification by building environments from scratch or using legacy flows; Collaborate with IP design, verification, and software teams to define requirements and review verification plans; Set up, deploy, migrate, maintain, and maximize the reuse of verification environments; Develop SystemVerilog UVM-based components and environments to execute feature-based verification plans; Debug failing tests, identify root causes, evaluate regressions, and enhance test cases to achieve 100% coverage; Improve development methodologies by applying artificial intelligence (AI) to increase efficiency.
