Senior Staff Engineer Verification
Core
Architecting complex module/subsystem/full chip testbenches and building verification infrastructure for ASIC verification.
Role type
Senior Staff IC ASIC verification engineer
Builds
Verification infrastructure and testbenches for complex SoCs/IPs
Domain
Semiconductor / ASIC Design
Required skills
SystemVerilog, UVM, Formal verification, Gate-level simulation, Power-aware verification, C modeling for DSP, Test plan creation, Technical leadership, Mentoring
Preferred skills
ARM-based SoC verification, RTL simulation, Ethernet (IEEE 802.3), MIPI protocols, DisplayPort
Technologies
SystemVerilog, UVM, C, RTL, Gate-level simulators
Responsibilities
Verify complex SoCs/IPs and provide technical leadership, Adopt state-of-the-art verification methods, Drive verification closure using SV/UVM, Develop C models for DSP and verification, Schedule management and cross-functional team interactions, Mentor and guide junior engineers
