Senior Principal Engineer - Digital Design
Core
Technical lead driving architecture, design, and delivery of complex digital IP, ASIC, and SoC solutions.
Role type
Senior Principal Engineer (Digital Design)
Builds
Complex digital IP, ASIC, and SoC solutions
Domain
Semiconductor / Digital IC Design
Required skills
SoC architecture, microarchitecture, RTL design (Verilog/System Verilog), PPA optimization, timing closure, DFT, low-power design, silicon bring-up, technical leadership
Preferred skills
Patent generation, technology strategy, risk mitigation
Technologies
Verilog, System Verilog, ASIC flows, SoC development flows
Responsibilities
Define and drive SoC/subsystem/IP architectures; Lead RTL design and implementation; Ensure successful execution across synthesis, timing closure, and power intent validation; Partner with verification teams for silicon success; Mentor senior engineers and establish engineering methodologies.
Seniority
Principal, strategic direction & mentorship
