Staff Engineer Analog Mixed signal verification
Core
Develop and validate behavioral models of analog IPs, create verification environments, and drive AMS verification for power management and mixed-signal designs.
Role type
Staff Engineer, Analog Mixed-Signal (AMS) Verification
Builds
Behavioral models, verification environments, and automated checkers for SoC-level analog IPs
Domain
Semiconductor / Power Management ICs / Mixed-Signal Design
Required skills
SystemVerilog Real Number Modeling (SV RNM), WREAL modeling, UVM Methodology, System Verilog Assertions (SVA), Analog/Mixed-Signal concepts (ADCs, LDOs, Buck/Boost), EDA tools (Cadence Virtuoso, Xcelium, APS, XPS), Python, Perl, Shell Scripting
Preferred skills
SoC-level AMS verification, verification planning and coverage closure, assertion-based verification techniques, regression management
Technologies
Cadence Virtuoso, Cadence Xcelium, APS, XPS, UVM, SystemVerilog, Python, Perl, Shell
Responsibilities
Develop and maintain SV RNM and WREAL models for analog and mixed-signal IPs; Verify and correlate RNM/WREAL models against transistor-level schematics; Create and deploy System Verilog Assertions (SVA); Perform SoC-level analog vector verification using DMS verification flows; Analyze simulation results, debug failures, and ensure comprehensive functional coverage; Develop automation frameworks and regression infrastructure using scripting languages; Collaborate with analog design teams to establish model-to-schematic correlation.
Seniority
Staff, hands-on IC
