Graduate - Analog Mixed-Signal Design Verification Engineer
Core
Develop verification plans, behavioral models, and testbenches for analog and mixed-signal device designs to ensure robustness and performance compliance.
Role type
Junior IC analog mixed-signal verification engineer
Builds
Mixed-signal verification flows and testbenches for device-level and system-level behavior
Domain
Semiconductor / Analog Mixed-Signal Design
Required skills
Verilog-AMS, SystemVerilog, mixed-signal verification concepts, testbench creation, simulation execution, corner analysis, fault injection, regression management
Preferred skills
Experience with Cadence Virtuoso, Cadence vManager, ADE Explorer/Assembler, Spectre, Xcelium
Technologies
Cadence Virtuoso, Cadence vManager, ADE Explorer/Assembler, Spectre, Xcelium
Responsibilities
Develop verification plans per device specifications; Generate and maintain Verilog-AMS and SystemVerilog behavioral models; Develop testbenches and simulation environments; Execute mixed-signal simulation flows; Evaluate behavior under nominal and corner conditions; Implement fault-injection and stress scenarios; Run and maintain regression suites
Seniority
Junior, entry-level graduate
