Senior Engineer Design
Core
Own and drive Static Timing Analysis (STA) flow and signoff methodology for HOBTO and Bixby Creek semiconductor platforms.
Role type
Senior IC STA Methodology Engineer
Builds
Production-quality STA solutions and scalable timing signoff methodologies for power systems and IoT chips
Domain
Semiconductor / Hardware Design
Required skills
STA flow ownership, MMMC setup, setup/hold analysis, OCV/AOCV/POCV implementation, SI-aware timing analysis, voltage-aware STA, Tcl scripting, Python scripting, Linux scripting, regression testing, QoR correlation analysis, tool qualification, cross-site collaboration
Preferred skills
Roadmap planning, issue resolution, reusable infrastructure design, automation solutions, regression frameworks, technical review representation
Technologies
Tcl, Python, Linux, Cadence, HOBTO, Bixby Creek
Responsibilities
Develop and maintain STA flows encompassing MMMC setup, setup/hold analysis, OCV/AOCV/POCV implementation, SI-aware timing analysis, and voltage-aware STA methodologies; Design, enhance, and support reusable STA infrastructure, automation solutions, and regression frameworks using Tcl, Python, and Linux scripting; Plan and execute regression testing for methodology updates and tool-version qualifications; Analyze QoR correlations and debug timing discrepancies; Collaborate with Physical Design, Design Signoff, and global R&D teams to deliver production-quality STA solutions; Represent the India STA Methodology team in technical reviews and lead cross-site collaboration
Seniority
Senior, hands-on IC
