Senior Staff Engineer Verification (f/m/div)
Core
Define verification strategy and infrastructure for digital or mixed-signal IP/Subsystem and SOC verification, developing scalable test benches and executing test plans.
Role type
Senior Staff Engineer Verification
Builds
Verification infrastructure, test benches, and test suites for semiconductor IP and SoC
Domain
Semiconductor / Digital and Mixed-Signal Verification
Required skills
System Verilog, UVM, OVM, constraint random verification, formal verification, functional coverage, code coverage, gate level simulation, mixed-signal design knowledge, automotive functional safety concepts
Preferred skills
ISO 26262 qualification experience, knowledge of protocols (AHB, AMBA, AXI, SPI, LIN, UART)
Technologies
System Verilog, UVM, OVM, Cadence, Synopsys
Responsibilities
Define verification strategy (constraint random, formal, directed), develop and debug random constraint verification test suites, participate in cross-functional collaboration with design and post-Silicon teams, identify and document test plans
Seniority
Senior Staff, hands-on IC
