Staff Engineer Design
Core
Leading and planning the modeling of analog/hard IP using Verilog and System Verilog, and developing modeling support for pre-silicon validation.
Role type
Staff Engineer, Analog/Digital IP Modeling
Builds
Analog and hard IP models, pre-silicon validation support
Domain
Semiconductor, Analog/Digital Integrated Circuits
Required skills
Verilog, System Verilog, UVM, AMS/Digital Block Modeling, RNM modeling, Mentorship
Preferred skills
MSV simulation flow, Analog circuit basics, Automation deployment, Formal verification
Technologies
Verilog, System Verilog, UVM, MSV
Responsibilities
Planning analog/hard IP modeling, Developing modeling support for pre-silicon validation, Mentoring junior engineers
Seniority
Staff, hands-on IC with mentorship
