Staff Engineer Digital Verification
Core
Create and define verification plans and develop verification environments for ICs using UVM and SystemVerilog.
Role type
Staff Engineer, Digital Verification
Builds
Verification environments and test scenarios for microcontroller-based ICs
Domain
Semiconductor / Digital Verification
Required skills
UVM, SystemVerilog, Constrained Random Verification, Formal Verification (Assertions), Metric Driven Verification, RTL design (VHDL), Microcontroller-based ICs, Security and safety requirements
Preferred skills
Cadence verification software
Responsibilities
Create and define verification plans, Develop verification environments for ICs, Draw on test scenarios using SystemVerilog, Verify functionality using the Constrained Random approach, Develop assertions in SystemVerilog for formal verification, Interact with other disciplines to define verification plans and strategies, Provide proactive support to users of the verification flow environment, Be responsible for verification methods
