Design Verification Manager
Core
Drive verification strategy and technical leadership for image sensor-based SoC programs, owning SoC-level verification architecture end-to-end and acting as the primary technical authority for verification sign-off.
Role type
Senior IC Design Verification Manager (SoC)
Builds
Image sensor-based System-on-Chip (SoC) products
Domain
Semiconductor / VLSI / Imaging SoC
Required skills
SystemVerilog, UVM methodology, functional coverage, assertion-based verification (SVA), formal verification (JasperGold), image sensor interfaces (MIPI CSI, I3C/I2C), SoC integration verification, Python/Perl/TCL scripting, Gate-Level Simulation (SDF)
Preferred skills
Emulation/FPGA prototyping, security/crypto IP verification, low-power verification (UPF/CPF), ISO 26262 experience, EDA vendor collaboration
Technologies
UVM, JasperGold, Python, Perl, TCL, MIPI CSI, I3C, I2C, SDF
Responsibilities
Define and own SoC verification strategy, architecture, and closure plan; Drive verification planning across IP, subsystem, and full-chip levels; Provide technical leadership on methodology, tooling, and reuse strategy; Review and approve verification plans, testbench architectures, and coverage models; Drive SoC-level integration verification (power-up, clocking, reset, interconnect, low-power); Champion formal verification for control-logic and connectivity; Own escalation and resolution of critical verification issues; Mentor and develop senior and mid-level verification engineers; Evaluate and drive adoption of new verification tools, flows, and AI-assisted techniques.
Seniority
Senior, hands-on IC with management responsibilities
