Senior Engineer -Performance Verification
Core
Top-level performance verification of complex high-performance ASICs and multi-chip-modules, ensuring they meet standards for throughput, latency, bandwidth, and security.
Role type
Senior IC ASIC Performance Verification Engineer
Builds
High-performance ASICs and SoCs for complex systems
Domain
Semiconductor / ASIC Design / High-Speed Interfaces
Required skills
RTL debugging (SystemVerilog/VHDL), C programming for embedded software, SystemC/TLM simulation, UVM VIP development, formal connectivity verification, gate-level simulation (GLS), high-speed protocol analysis (PCIe, Ethernet, AXI, DDR, UCIe), NoC/Interconnect architecture knowledge, CI/CD flow scripting
Preferred skills
Multi-core design experience, HW/SW co-debugging, CoreSight/JTAG, HW emulation (Siemens Veloce, Cadence Palladium), power-aware verification, XPROP, timing-aware GLS, silicon bring-up lab experience
Technologies
SystemVerilog, VHDL, C, SystemC, TLM, UVM, PCIe, Ethernet, AXI, DDR, UCIe, AMBA, Cadence STG/IWB, Siemens Veloce, Cadence Palladium, XPROP
Responsibilities
Analyze RTL performance metrics (throughput, latency, QoS, cache efficiency), implement performance verification plans at SoC-level, debug RTL designs using simulation/emulation tools, collaborate with architecture/design teams on performance requirements, optimize system performance (DDR, CPU, Interconnects), develop tests involving UVM VIPs, maintain TLV CI flow and visualize results
Seniority
Senior, hands-on IC
