Research Engineer, Chip Design RL
Core
Design RL environments and evaluations for agentic RTL generation, design verification, and physical design optimization to advance AI models' ability to design silicon.
Role type
Senior IC research engineer (chip design RL)
Builds
RL environments, evaluations, and training runs for hardware design tasks
Domain
AI safety / Reinforcement Learning / Chip Design (ASIC/FPGA)
Deliverable
production ML models
Required skills
ASIC or FPGA design, RTL, design verification (UVM, formal methods), physical design (synthesis, place-and-route), PPA optimization, DFT, ECOs, EDA tools, tape-out experience
Preferred skills
Reinforcement learning, evaluations or environments, tooling or automation around chip design flows, ML accelerators, high-level synthesis, architecture simulators
Technologies
UVM, formal methods, EDA tools
Responsibilities
Invent, design, and implement RL environments and evaluations; Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards; Conduct experiments and shape roadmap; Deliver work into research and production training runs; Collaborate with researchers and engineers
Seniority
Senior, hands-on IC
