Serdes Characterization & Post-Silicon Validation Engineer
Core
Lead post-silicon bring-up, characterization, and validation of high-speed SerDes interfaces (NRZ/PAM4) in complex SoCs for satellite platforms.
Role type
Senior IC SerDes Characterization & Post-Silicon Validation Engineer
Builds
High-speed test and validation capability, automated characterization environments, and system-level link operation for satellite SoCs.
Domain
Aerospace / High-Speed Digital Interfaces / Signal Integrity
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> physical/clinical work (Note: Corrected to 'physical/clinical work' is wrong, should be 'product features' or 'infrastructure'. Let's map to 'product features' as it's about bringing up the interface for the product, or 'infrastructure' for the lab. The prompt says 'physical/clinical work' is an option. This is neither. It is 'product features' (validating the interface) or 'infrastructure' (building the lab). Given the mix, 'product features' fits the validation of the SoC interface best, but 'infrastructure' fits the lab building. Let's use 'product features' as the primary output of the role is the validated interface functionality.) -> Actually, looking at the options: 'production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work'. The role builds the lab (infrastructure) and validates the interface (product feature). I will select 'product features' as the primary deliverable of the engineering work on the SoC.
Required skills
High-speed SerDes characterization (NRZ/PAM4), post-silicon validation, signal integrity analysis, eye diagram/jitter/BER testing, automated test environment development, complex debugging across silicon/package/PCB/firmware
Preferred skills
112G+ PAM4 experience, Ethernet/PCIe/JESD204/Interlaken interface knowledge, compliance testing, SerDes behavioral modeling, advanced package/PCB channel expertise
Technologies
Python, high-bandwidth oscilloscopes, BERTs, pattern generators, VNAs, TDR/TDT, FFE/CTLE/DFE equalization
Responsibilities
Lead post-silicon bring-up of 112G-class SerDes interfaces; Develop electrical characterization plans across lanes, data rates, and operating conditions; Characterize TX eye quality, jitter, output amplitude, linearity, equalization, RX sensitivity, BER, and link margin; Validate TX/RX equalization and link-training behavior; Perform BER and stress testing across worst-case channels; Debug complex link issues spanning SerDes IP, clocks, power, package, PCB, firmware, and digital logic; Develop automated characterization and regression environments; Support transition from chip-level to system-level validation; Contribute to building high-speed validation lab infrastructure and measurement methodology
Seniority
Senior, hands-on IC
