Serdes Characterization & Post-Silicon Validation Engineer
Core
Lead post-silicon bring-up, characterization, and validation of high-speed SerDes interfaces (NRZ/PAM4) in complex SoCs for satellite platforms.
Role type
Senior IC SerDes Characterization & Post-Silicon Validation Engineer
Builds
High-speed test and validation capability, automated characterization environments, and system-level link operation for satellite SoCs.
Domain
Aerospace / High-Speed Digital Interfaces / Signal Integrity
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
High-speed SerDes characterization, post-silicon validation, signal integrity analysis, eye diagram analysis, jitter decomposition, BER testing, automated test environment development, Python scripting, cross-domain debugging (silicon/package/PCB/firmware)
Preferred skills
112G+ PAM4 SerDes, Ethernet/PCIe/JESD204/Interlaken interfaces, compliance testing, SerDes behavioral modeling, third-party IP integration, advanced package/PCB channel analysis, PLL/clocking noise effects
Technologies
NRZ, PAM4, FFE, CTLE, DFE, VNAs, BERTs, TDR/TDT, Python
Responsibilities
Lead post-silicon bring-up of 112G-class SerDes interfaces; Develop electrical characterization plans across lanes, data rates, and operating conditions; Characterize TX eye quality, jitter, equalization, RX sensitivity, and link margin; Validate TX/RX equalization and link-training behavior; Perform BER and stress testing across worst-case channels; Debug complex link issues spanning SerDes IP, clocks, power, package, PCB, and firmware; Correlate silicon measurements with SerDes models and simulations; Develop automated characterization and regression environments; Support transition from chip-level to system-level validation; Contribute to building high-speed validation lab infrastructure and methodology
Seniority
Senior, hands-on IC
