Principal ASIC Physical Design Engineer
Core
Lead the full RTL-to-GDSII physical design flow for complex mixed-signal SoCs destined for next-generation high-power satellites.
Role type
Principal ASIC Physical Design Engineer
Builds
High-performance SoCs for satellite and space systems (via careerplan.io/jobs/5288635008-principal-asic-physical-design-engineer-at-k2spacecorporation)
Domain
Aerospace / Semiconductor Physical Design
Deliverable
production ML models | product features
Required skills
RTL-to-GDSII flow ownership, timing closure, IR drop analysis, ECO implementation, multi-clock/multi-voltage SoC constraints, advanced FinFET process nodes, external vendor management, DFT integration, power domain implementation (UPF/CPF)
Preferred skills
radiation-hardened ASICs, chip-package co-design, advanced packaging (2.5D/3D), TSMC tapeout experience, GAA technologies
Technologies
Synopsys, Cadence, Siemens, TSMC
Responsibilities
Own complete RTL-to-GDSII flow including synthesis, floorplanning, place & route, CTS, STA, and physical verification; Develop and maintain physical design methodologies and automation; Collaborate with front-end and verification teams for clean handoffs and timing closure; Drive timing closure across multiple voltage and process corners; Partner with package, SI/PI, and test teams for chip-to-board integration; Manage and guide external physical design partners and service vendors; Work with EDA vendors to debug and optimize tool flows; Support chip bring-up and debug with post-silicon and test teams
Seniority
Principal, hands-on IC with mentorship
