Sr. Engineer, SoC Design Verification Engineer, System Management Controller
Core
Design and execute verification tests for the System Management Controller (SMC) to enable seamless multi-chip integration in chiplet-based SoCs.
Role type
Senior IC SoC Design Verification Engineer (System Management Controller)
Builds
Scalable multi-die systems and chiplet-based SoCs
Domain
Semiconductors / AI Hardware / Chiplet Architecture
Deliverable
production ML models | product features
Required skills
SystemVerilog, SV-UVM, Python, C/C++, test plan development, hardware/software flow debugging, AI-assisted tool usage (Copilot, Cursor, Claude)
Preferred skills
Knowledge of UCIe and BoW interconnect standards, co-simulation methodologies (Cocotb)
Technologies
SystemVerilog, SV-UVM, Python, C/C++, Cocotb, UCIe, BoW
Responsibilities
Develop and maintain SMC tests and supporting DV infrastructure; Write, execute, and track test plans for chiplet and multi-chip SoC designs; Use C/C++ to develop tests compiled, loaded, and executed directly on the DUT; Triage, analyze, and debug issues in close collaboration with design and architecture teams
Seniority
Senior, hands-on IC
