System IP RTL Design Lead
Core
Lead the definition, selection, and integration of complex datacenter-class System IP and SoC architectures for next-generation semiconductor products.
Role type
Senior IC System IP RTL Design Lead
Builds
High-performance RISC-V CPU and AI compute platforms
Domain
Semiconductor / AI Hardware / SoC Architecture
Deliverable
production ML models
Required skills
System IP and SoC architecture, RTL design and debug (Verilog/SystemVerilog), high-speed protocols (AXI/AHB/APB, PCIe, DDR, USB), PPA optimization, hierarchical debugging, IP integration, formal verification, scripting (Python/Tcl), UVM
Preferred skills
Microarchitecture decision-making, pre-silicon simulation, emulation, post-silicon bring-up, cross-functional collaboration
Technologies
Verilog, SystemVerilog, Python, Tcl, UVM, AXI, AHB, APB, PCIe, DDR, USB
Responsibilities
Lead technical definition and integration of internal and third-party IPs (MMUs, Interrupt controllers, Interconnects, Memory controllers, peripherals); Define system-level requirements and IP specifications to achieve PPA goals; Drive IP design through sign-off ensuring functional, security, and quality compliance; Debug complex logic across hierarchical levels in simulation, emulation, and bring-up environments.
Seniority
Senior, hands-on IC
