Sr. Engineer/Staff Engineer, Design Verification,System IP
Core
End-to-end verification of IOMMU (Input/Output Memory Management Unit) IP to ensure functional correctness and performance for AI/ML systems.
Role type
Senior Design Verification Engineer (ASIC/SoC)
Builds
High-performance RISC-V CPU and memory-management IPs for AI platforms
Domain
Semiconductor / AI Hardware / System-on-Chip
Deliverable
production ML models
Required skills
SystemVerilog, UVM, constrained-random verification, coverage analysis, regression debugging, AXI/ACE/CHI/PCIe protocols, Python/TCL/Bash scripting
Preferred skills
Block or subsystem-level verification ownership, automation workflow improvements, cross-functional collaboration
Technologies
SystemVerilog, UVM, Python, Perl, TCL, Bash, AXI, ACE, CHI, PCIe
Responsibilities
Own block or subsystem-level verification from test planning to sign-off, build verification environments from scratch, drive coverage closure, debug complex design and verification issues
Seniority
Senior, hands-on IC
