SoC Debug and Trace Architect
Core
Define and scale debug and trace capabilities across CPU and AI silicon product lines to enable performance validation and issue diagnosis.
Role type
SoC Debug and Trace Architect
Builds
Debug and trace infrastructure for RISC-V CPU and AI silicon
Domain
Semiconductor hardware design and verification (CPU/SoC/ASIC)
Deliverable
infrastructure
Required skills
hardware debug for CPU/SoC/ASIC, processor architecture (RISC-V/x86/ARM), debug and trace methodologies (iJTAG), HDL (Verilog/VHDL), Python, Git
Preferred skills
silicon bring-up experience, post-silicon validation, firmware and driver interaction
Technologies
RISC-V, x86, ARM, iJTAG, Verilog, VHDL, Python, Git
Responsibilities
Define and implement scalable debug architecture, design and validate hardware debug features, prove debug capabilities during silicon development, support silicon bring-up, collaborate with hardware and software teams
Seniority
Experienced IC
