Senior SOC Debug Verification Engineer
Core
Own verification of Design for Debug (DFD) SoC level flows, develop verification strategies and environments, run tests, debug failures to root cause, and support post-silicon validation.
Role type
Senior IC SoC Debug Verification Engineer
Builds
SoC debug architectures, verification plans, test benches, checkers, and coverage metrics
Domain
Semiconductor / SoC Design / Debug Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SoC verification, DFD verification, test plan development, test generation, debugging, coverage signoff, JTAG interface, hardware triggers, breakpoints, tracing, ARM CoreSight components, ARM AMBA protocols, post-silicon validation support, generative AI for verification
Preferred skills
CPU/SOC design experience, Agile practices, technical leadership, mentoring
Technologies
JTAG, ARM CoreSight (DAP, CTI, ETIM, TPIU), ARM AMBA (AXI, ACE, CHI)
Responsibilities
Develop verification strategy, requirements, environments, tools, and methodologies; Write test plans and implement tests, test generators, test benches, checkers, and coverage; Run tests and debug failures to root cause; Provide technical guidance and mentorship to other engineers; Support post-silicon validation plans, tests, and debug; Apply generative AI solutions to verification work
Seniority
Senior, hands-on IC
