Sr. CAD Engineer
Core
Modernize and upgrade design environment, EDA infrastructure, and in-house CAD tools for advanced semiconductor technology nodes while supporting design and verification activities.
Role type
Senior IC CAD Engineer (Physical Design & Verification)
Builds
In-house CAD tools, EDA infrastructure, and SoC/mixed-signal designs (via careerplan.io/jobs/51-00F-F8-E60-sr-cad-engineer)
Domain
Semiconductor / IC Design / Physical Verification
Required skills
C/C++ programming, TCL scripting, Python scripting, Linux shell scripting, Physical Layout Verification, LVS/DRC/ERC/Antenna/PERC signoff checks, SoC design flows, mixed-signal design flows, EDA tool expertise (Synopsys, Cadence, Siemens EDA), Git-based development flows
Preferred skills
Siemens Calibre verification flows, RC extraction (StarRC, Calibre xACT), Generative AI tools for automation
Technologies
Synopsys, Cadence, Siemens EDA, Calibre, StarRC, Calibre xACT, Git, C, C++, TCL, Python, Linux
Responsibilities
Upgrade EDA infrastructure and in-house CAD tools, support design and verification activities for current and future semiconductor projects, debug complex signoff checks on SoC and mixed-signal designs
Seniority
Senior, hands-on IC
