Principal SerDes Bring-up Validation Engineer
Core
Lead end-to-end post-silicon bring-up, validation, and characterization of high-speed SerDes and retimer silicon for rack-scale AI connectivity infrastructure.
Role type
Principal SerDes Bring-up Validation Engineer (Hands-on IC)
Builds
Automated test frameworks, characterization flows, and validation reports for high-speed PHYs and retimers.
Domain
Semiconductor hardware validation, high-speed serial interfaces, AI infrastructure connectivity.
Required skills
Post-silicon bring-up and characterization, mixed-signal high-speed lab environments, NRZ and PAM4 architectures, high-speed building blocks (PLLs, CTLE, DFE, FFE), retimer debugging and equalization tuning, Python and C/C++ programming, signal integrity (SI) and power integrity (PI) analysis, waveform analysis, protocol analyzer usage.
Preferred skills
MS or PhD in Electrical Engineering, advanced signal integrity test equipment proficiency, IEEE 802.3 Ethernet standards knowledge, serial interface experience (I2C, I3C, SPI, UART), SI/PI simulation translation.
Technologies
BERTs, real-time oscilloscopes, sampling scopes, TDRs, VNAs, protocol analyzers, Python, C/C++.
Responsibilities
Design and execute bring-up plans for silicon blocks; drive design reviews to ensure testability; perform functional and parametric testing and performance benchmarking; build scalable test automation and data analysis pipelines; diagnose complex failures across analog, digital, and protocol layers; root-cause cross-domain failures using lab measurements; document findings and improve methodologies; develop test software and platform integrations; measure and communicate validation impact to stakeholders.
Seniority
Principal, hands-on IC with mentorship
