Tech Lead– Verification Methodology/CAD
Core
Build scalable verification frameworks, automate verification workflows, and drive methodology across IP and SoC verification teams.
Role type
Senior IC verification methodology and automation lead
Builds
Scalable simulation, regression, and coverage infrastructure for large-scale SoC/IP verification
Domain
Semiconductor hardware verification (VLSI/SoC)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verification methodology, CAD, automation, Python, Tcl, Perl, Shell, C++, SystemVerilog, UVM, regression infrastructure, coverage analysis, Linux/Unix, EDA tool integration
Preferred skills
Large-scale SoC/IP verification, CI/CD infrastructure, distributed/parallel regression, cloud-based compute environments, database/API/web-based verification infrastructure
Technologies
Python, Tcl, Perl, Shell, C++, SystemVerilog, UVM, VCS, Xcelium, Questa, Jenkins, GitLab CI
Responsibilities
Own and drive verification methodology and infrastructure; Develop scalable frameworks for simulation, regression, coverage, debug, and signoff; Build and maintain verification CAD/automation flows; Automate test generation, compilation, regression execution, result collection, coverage analysis, and reporting; Develop infrastructure for large-scale UVM/SystemVerilog verification environments; Improve simulation and regression turnaround time through parallelization and optimization; Integrate simulation, lint, CDC/RDC, formal, coverage, and other verification tools into common workflows; Develop dashboards and metrics for verification quality, coverage, regression health, and project status; Debug infrastructure and tool-flow issues and provide rapid support to verification teams; Establish reusable verification components, scripts, libraries, and methodology guidelines; Drive adoption of best practices across multiple verification teams; Evaluate new verification technologies and tools and recommend improvements; Work closely with EDA vendors to troubleshoot tool issues and improve flows; Support migration and integration of new EDA tool versions and methodologies; Develop documentation and training for verification teams; Mentor verification CAD/methodology engineers and provide technical leadership
Seniority
Senior, hands-on IC with leadership responsibilities
