Principal Design Verification Engineer
Core
Functional verification of complex SoC/silicon products for server, storage, and networking applications, focusing on PCIe and CXL protocols.
Role type
Principal Design Verification Engineer
Builds
Functional verification plans, test sequences, VIP abstraction layers, and coverage reports for AI infrastructure connectivity chips.
Domain
Semiconductor hardware design, AI infrastructure, high-speed interconnects (PCIe, CXL)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM methodology, PCIe/CXL protocol specifications, VIP development, assertion writing, coverage analysis, test sequence generation, simulation environment management, SoC verification
Preferred skills
Physical/Link/Transaction layer expertise, QoS buffering/queuing, NOC-based SoC verification, system-level performance analysis
Technologies
UVM, PCIe, CXL, QoS, NOC
Responsibilities
Develop block-level and system-level verification plans; write and execute test sequences; collaborate with RTL designers to debug failures; create VIP abstraction layers; write assertions and analyze coverage data.
Seniority
Principal, hands-on IC
