Fabric Modeling and Analysis Engineer for Scale Up Fabric (2026-325)
Core
Design, implement, and validate high-fidelity performance models for rack-scale AI interconnect fabrics (Scorpio) to predict bandwidth, latency, and throughput ceilings before silicon tape-out.
Role type
Senior IC fabric modeling and analysis engineer
Builds
Transaction-level and cycle-approximate system models for scale-up fabrics
Domain
AI/ML infrastructure, high-speed interconnects, network architecture
Deliverable
production ML models | product features
Required skills
Python, C++, cycle-approximate/event-driven simulation, fabric modeling frameworks (Astera-Sim, Garnet, NS-3, ATLAHS, BookSim), high-speed interconnect protocols (PCIe Gen 6/7, ESUN, UALink), cluster scalability analysis, AI/ML collective communication patterns
Preferred skills
MS/PhD in EE/CS, LLM traffic pattern analysis, model-silicon correlation, competitive architecture analysis, IP/patent generation
Technologies
Astera-Sim, Garnet, NS-3, ATLAHS, BookSim, PCIe, ESUN, UALink
Responsibilities
Design and maintain AI/ML system simulators supporting collective communication and traffic management; calibrate models against benchmark data; develop theoretical roofline models to identify compute vs. fabric-bound regimes; model fabric performance across clusters scaling to thousands of GPUs; analyze emerging interconnect technologies (UALink, optical fabrics) for roadmap influence.
Seniority
Senior, hands-on IC
