Senior/ Staff Front-End CAD Engineer
Core
Architecting methodologies, automation scripts, and design flows for front-end semiconductor chip design to enable hardware teams to push silicon performance limits.
Role type
Senior/Staff IC Front-End CAD Engineer (VLSI)
Builds
Automated RTL generation tools, IPs, SoC schemes, and EDA integration workflows for next-generation processors.
Domain
Semiconductor hardware design / VLSI / AI infrastructure
Deliverable
production ML models | product features | infrastructure
Required skills
Python, Tcl, Verilog, System Verilog, EDA tool integration, Linux/Unix environment, automation scripting
Preferred skills
VLSI design cycle knowledge, clock domain crossing, simulation, debugging, synthesis, timing analysis, linting, Git, cluster management (LSF/SGE)
Technologies
Python, Tcl, Verilog, System Verilog, Cadence, Synopsys, Mentor Graphics, Git, LSF, SGE
Responsibilities
Develop and optimize RTL generation tools; Create robust applications for model build, regression, and analysis; Evaluate and integrate EDA tools; Define methodologies and integrate AI tools into VLSI development flows.
Seniority
Senior/Staff, hands-on IC
