CareerPlan

Layout/Mask Designer

Boise, Idaho, United States of AmericaFull-time2026-11-04 → 2026-11-10

Core

Create physical layout of transistors, resistors, and capacitors for analog circuits used in memory product development, including floor planning, routing, and power bus designs.

Role type

IC Layout/Mask Designer

Builds

Memory products (DRAM)

Domain

Semiconductor / Analog IC Design

Required skills

DRAM circuit functions, IC custom layout for IP design, Cadence OA, Caliber verification tools, DRC, LVS, layout pattern creation, industrial application of devices and sensors

Technologies

Cadence OA, Caliber

Responsibilities

Create physical layout of transistors, resistors, and capacitors for analog circuits; Build layouts meeting process rules and verifying schematic match; Perform floor planning, routing, and power bus designs; Perform layout verification (LVS/DRC/DFM); Communicate with engineering teams across India, Japan, and US.

Seniority

Mid-Senior, hands-on IC