Senior Engineer - HIG HBM - PE Design Validation
Core
Senior engineer performing design validation, root cause analysis, and data analysis for High Bandwidth Memory (HBM) products in the semiconductor industry.
Role type
Senior IC validation engineer (semiconductor)
Builds
HBM memory packages (DRAM + logic chips via TSV) for ML/AI applications
Domain
Semiconductor / Memory / VLSI
Deliverable
production ML models
Required skills
VLSI design, semiconductor process knowledge, device physics, schematic & layout, simulation, data analysis, hardware/software debugging, Verilog/VHDL/System Verilog, JEDEC specifications
Preferred skills
AI tool integration, statistical analysis, innovation in validation procedures
Technologies
ATE/bench analysis, simulation tools, statistical tools, Verilog, VHDL, System Verilog, TSV
Responsibilities
Interface between Design, Manufacturing, Test, and Quality teams; Perform validation on test modes and designs using simulation and data analysis; Resolve manufacturing/test/quality issues via debugging and circuit simulation; Analyze engineering data for validation and risk assessment; Create internal architecture documentation based on JEDEC specs; Identify and share AI-enabled enhancements for efficiency.