High Bandwidth Memory Design Architect - E1 to SMTS
Core
Analyze, model, and pathfind next-generation High Bandwidth Memory (HBM) architectures to optimize performance, power, area, thermal behavior, and reliability for AI and high-performance computing systems.
Role type
Senior IC semiconductor architecture engineer (HBM)
Builds
Scalable, high-performance HBM solutions for AI, HPC, and cloud infrastructure
Domain
Semiconductor / Memory Systems / Advanced Packaging
Deliverable
production ML models
Required skills
CMOS circuits, analog/mixed-signal design, memory systems, computer architecture, thermal sciences, signal integrity, power delivery, engineering modeling, simulation, data analysis
Preferred skills
HBM/DRAM/SRAM architecture, 3D integration, high-speed interfaces, AI/LLMs for engineering, HSPICE/FineSim/Spectre, technical publications
Technologies
HSPICE, FineSim, Spectre, AI/LLMs, Generative AI
Responsibilities
Analyze HBM/DRAM architectures using models and simulations to evaluate timing, bandwidth, power, and thermal performance; Develop modeling methodologies to assess architectural approaches and support technology pathfinding; Collaborate with circuit, layout, packaging, and system teams on implementation feasibility and tradeoffs; Perform root-cause analysis to validate assumptions and improve model accuracy; Communicate technical findings and design recommendations to multidisciplinary teams
Seniority
Senior, hands-on IC
