CareerPlan

Senior Design Verification Engineer

San Jose, California, United States of AmericaFull-time$130k2026-10-16 → 2026-11-10

Core

Develop and support CAD tools, automation, and flows for custom IC design, layout, simulation, and verification, integrating AI/ML to improve engineering productivity and design quality.

Role type

Senior IC CAD/EDA engineer (AI-enabled)

Builds

Custom memory products (DRAM, HBM, NAND) via automated design and verification flows

Domain

Semiconductor / Memory / EDA

Deliverable

production ML models

Required skills

Python, SKILL, Tcl, Perl, C, C++, Linux/Unix shell scripting, CMOS/VLSI fundamentals, EDA tool integration, debugging, technical mentorship

Preferred skills

Cadence Virtuoso, Calibre DRC/LVS, Spectre/HSPICE/FineSim, Fusion Compiler/Innovus/PrimeTime, StarRC/Quantus, AI/ML in engineering workflows, source control, DRAM/HBM/NAND knowledge

Technologies

Cadence Virtuoso, Calibre, Spectre, HSPICE, Fusion Compiler, Innovus, PrimeTime, Formality, StarRC, Quantus, Python, SKILL, Tcl, Perl, C, C++