Staff Engineer IP Verification - Digital Design Verification
Core
Lead verification efforts for strategic IPs and complex subsystems in DDR5, LPDDR5, DDR6, and LPDDR6 memory technologies operating at high speeds up to 11,400 MT/s.
Role type
Staff-level IC digital design verification engineer
Builds
Custom block-level memory designs for high-performance DRAM architectures
Domain
Semiconductor / Memory / Digital Design
Required skills
RTL verification, SV-UVM, digital simulation tools, functional coverage analysis, root cause debugging, scripting (Perl/Python), team leadership, technical roadmap definition
Preferred skills
AI tool adoption for verification workflows, experience with Virtuoso/Xcellium/Simvision/Verdi/Verisium
Technologies
SV, UVM, Perl, Python, Virtuoso, Xcellium, Simvision, Verdi, Verisium
Responsibilities
Define verification scope and strategy for block/chip RTL; Develop and maintain verification testbenches and test vectors; Run directed and constrained-random tests and regressions; Close verification metrics (functional/code coverage) and identify verification holes; Debug RTL/testbench/environment issues and partner with design engineers; Provide verification status and risk summaries to stakeholders
Seniority
Staff, hands-on IC with mentorship and technical leadership
