Principal Engineer, ASIC Physical Design
Core
Lead physical design implementation for processors, controllers, and ASICs in the Enterprise SSD Group, focusing on low-power floorplanning, timing closure, and tape-out.
Role type
Principal IC Physical Design Engineer
Builds
Enterprise SSD processors, controllers, and ASICs
Domain
Semiconductor / Memory and Storage
Deliverable
production ML models
Required skills
Block-level low-power floorplanning, placement, clock tree synthesis, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC, APR flow development, PPA analysis, Ansys Redhawk-SC, Cadence Innovus/Tempus, Caliber physical verification, digital electronics fundamentals, microprocessor architecture, AI tool usage for design closure
Preferred skills
Advanced process nodes (5nm/3nm), Cadence PnR tools, formal verification, digital electronics and microprocessors experience
Technologies
Ansys Redhawk-SC, Cadence Innovus, Cadence Tempus, Caliber, Claude, MS Copilot
Responsibilities
Perform block and full-chip STA closure, close IR issues based on feedback, lead team for sub-system partition closure deliverables, execute tape-out activities
Seniority
Principal, hands-on IC with leadership
