Mixed Signal SVE Engineer
Core
Lead bring-up, debugging, and optimization of DDR/SerDes PHYs across post-silicon teams to ensure successful product launches.
Role type
Senior IC mixed-signal silicon validation engineer
Builds
Wireless ICs (DDR/SerDes PHYs) for mobile devices
Domain
Semiconductor / Wireless Connectivity
Deliverable
production ML models
Required skills
DDR/SerDes test development, firmware development, Python scripting, PHY circuitry fundamentals, signal integrity analysis, lab instrumentation, statistical modeling, data visualization, automated pipeline development
Preferred skills
Machine learning for hardware validation, AI for lab instrumentation workflows, soldering, system instrumentation
Technologies
Python, Oscilloscopes, Spectrum analyzers, Logic analyzers
Responsibilities
Lead bring-up and debugging of DDR/SerDes PHYs, Develop firmware and execute regression testing, Generate test reports and documentation, Provide post-release support for customer issues, Identify and resolve complex silicon issues, Build automated pipelines for data collection and model training
Seniority
Senior, hands-on IC
