Next Gen, High-Speed, Memory and Cache Controller Design Engineer
Core
Design and implement high-speed memory and cache controllers (HBM, LPDDR, DDR) for next-generation SoCs, interfacing with CPU, GPU, and DSP.
Role type
Senior ASIC Design Engineer (Memory/Cache Controller)
Builds
High-performance, low-power memory subsystems for Qualcomm mobile and computing products
Domain
Semiconductor / SoC Design / Memory Interfaces
Required skills
RTL coding, memory controller architecture, NoC, timing closure, synthesis, physical design support, gate-level simulation, power analysis, x86/ARM architecture knowledge
Preferred skills
HBM design, SRAM/L3 cache controller design, micro-architecture development
Technologies
RTL, HBM, LPDDR, DDR, NoC, SRAM, L3 cache, x86, ARM
Responsibilities
Develop architecture and design specifications for memory controllers; implement RTL code; debug designs and provide support during integration; contribute to design methodology improvements
Seniority
Senior, hands-on IC
