DDR Validation Engineer, Staff
Core
Lead end-to-end validation of next-generation LPDDR5X and LPDDR6 memory subsystems on AI Accelerator and Flagship mobile platforms, covering bring-up, performance, stress, debug, and production readiness.
Role type
Staff DDR Validation Engineer
Builds
High-quality silicon validation for SoCs across premium mobile, data center, and AI accelerator platforms
Domain
Semiconductor / SoC Validation / Memory Subsystems
Required skills
DDR memory subsystem validation, LPDDR4/5/5X/6 architecture, DDR controllers and PHYs, memory training and calibration algorithms, cache/coherency/NoC architectures, post-silicon debug, C/C++ low-level software development
Preferred skills
Mobile SoC/AI compute/automotive/server platform validation, SI/PI analysis, memory performance tuning, thermal characterization, first-silicon memory bring-up, volume production qualification
Technologies
LPDDR5X, LPDDR6, FPGA, emulation platforms, C/C++
Responsibilities
Define and execute DDR validation strategy across emulation, FPGA, and silicon platforms; Drive LPDDR5X/LPDDR6 bring-up, training validation, frequency scaling, low-power state validation, and feature enablement; Develop and execute validation plans covering memory functionality, performance, reliability, power, and corner-case scenarios; Lead debug of DDR controller, PHY, firmware, SI/PI, timing, and system-level issues; Validate interactions between DDR, CPU, GPU, NPU, cache hierarchy, NoC, and system software; Drive bandwidth, latency, QoS, memory pressure, and AI workload characterization; Develop scalable automation, regression infrastructure, and debug analytics frameworks; Partner with Architecture, Design, Firmware, SI/PI, Package, and DRAM vendors to root-cause and resolve issues.
Seniority
Staff, hands-on IC
