FY27 Intern - Soft IP ASIC Engineering Internship - Canada (12 or 16 months)
Core
Intern contributing to the design and verification of ASIC IP blocks and sub-systems for connectivity technologies.
Role type
ASIC Engineering Intern
Builds
Standards-compliant IP blocks for Ethernet, UALink, UEC, ESUN, CXL, and PCIe FPGAs/ASICs
Domain
Semiconductor / Connectivity / Hardware Design
Required skills
Python, Perl, TCL, Unix/Linux Shell scripting, Source code revisioning systems (SVN, CVS, RCS)
Preferred skills
Digital logic design, Verilog/VHDL, ASIC/FPGA flows, Debugging tools
Technologies
SystemVerilog, UVM, Verilog, Ethernet, UALink, UEC, ESUN, CXL, PCIe
Responsibilities
Develop and document verification environments using SystemVerilog and UVM, Develop and document designs using Verilog, Execute individual testcases against RTL, Issue and track bug reports from inception to closure, Develop scripts to augment development process
Seniority
Intern
